Differential output circuit

ABSTRACT

A differential output circuit for generating a bipolar DC current for an armature winding without requiring a bipolar power source. A combination of transistors and resistors are utilized to effectively apply a bipolar driving current. The use of only transistors and resistors in the differential output circuit enables its easy implementation as an integrated circuit.

BACKGROUND OF THE INVENTION

This invention relates to a differential output circuit. An embodiment of the invention will be described relative to an output circuit for driving a brushless DC motor, and especially to a full wave drive output circuit.

A drive circuit for a brushless motor may be divided into half-wave drive circuits and full wave drive circuits. The half-wave drive causes a unidirectional DC current to flow in each armature winding to generate torque. The full-wave drive circuit causes a DC current to flow in the normal and reverse directions in each armature winding so as to thereby generate torque.

Conventionally, in the full-wave drive circuit case, each armature winding is provided with a common terminal so that positive and negative power sources, with respect to the common terminal, respectively feed currents in the normal and reverse directions to the armature winding.

FIG. 1 shows a conventional example of a two-phase full-wave drive circuit, in which armature windings 9 and 15 are grounded at the common terminals and supply voltages +V_(cc) and -V_(cc) are supplied to the circuit.

In FIG. 1, armature windings 9 and 15 are positioned in a relationship of being mutually shifted by an electrical angle of 90°. With respect to the respective windings, Hall generators 3 and 11 are disposed for detecting the rotor position. The Hall generators 3 and 11, as shown in FIG. 2, generate output voltage 16 and 17 which are shifted in phase by 90° and following the rotation of the rotor. The outputs are amplified by amplifiers 6 and 12 so as to be proportional to voltages at both ends of armature windings 9, 15 by means of a feedback circuit. Hence, voltage wave forms at terminals 8, 14 of armature windings 9, 15 with respect to ground terminals become similar to wave forms of the output voltages 16, 17. Other than the phase relation, both two phases act similarly, whereby the following description will concern single phase.

When terminal 8 of armature winding 9 is positive, transistor Q₁₀₁ is active and Q₁₀₂ is cut-off, and when negative, transistor Q₁₀₂ is active and Q₁₀₁ is cut-off to thereby respectively cause the flow of normal and reverse currents. In other words, the ground terminals act as the neutral point with respect to the positive and negative power sources. In this instance, only one power source is used once notwithstanding the fact that both positive and negative power sources are required with respect to the neutral point. Hence, there is a defect of reducing the voltage utility percentage of the single power supply to half.

SUMMARY OF THE INVENTION

The object of the present invention is to provide a differential output circuit for generating a bipolar DC current in an armature winding without requiring a bipolar power source.

BRIEF DESCRIPTION OF THE DRAWINGS

To completely eliminate the abovenoted defect of the prior art, this invention has been designed. The present invention will be discussed below in detail in accordance with the accompanying drawings, in which:

FIG. 1 is a block diagram of a conventional brushless motor drive circuit employing an output circuit having a neutral point;

FIG. 2 is a view showing waveforms of a rotor position detecting Hall generator and an armature winding;

FIG. 3 through FIG. 11 show embodiments of the invention, in which

FIG. 3 is a circuit diagram of an output circuit thereof;

FIG. 4 is a view explanatory of the output circuit using switches to be changed-over;

FIG. 5 is a block diagram of an output circuit using an integrated circuit;

FIG. 6 is a block diagram of an output circuit using current mirrors;

FIG. 7 is a block diagram of an output circuit using NPN transistors for switches;

FIG. 8 is a block diagram of an output circuit using composite transistors for switches,

FIG. 9 is a view explanatory of the circuit in FIG. 8;

FIG. 10 is a view explanatory of the output circuit using switches to be changed-over; and

FIG. 11 is a block diagram of an output circuit using a load current detecting resistor.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 3 shows an embodiment of a differential output circuit of this invention, in which input terminals 20 and 21 are respectively connected to inputs 22 and 23 of two-phase differential amplifier 27 by way of resistors R₁ and R₃. Two-phase outputs 24 and 25 of two-phase differential amplifier 27 are respectively fed back to the inputs 22 and 23 through resistors R₂ and R₄. A load is connected between outputs 24 and 25, e.g., armature winding 26. Supply voltage +V_(cc) is supplied to the two-phase differential amplifier 27. The relationship between the input and the output of the two-phase differential amplifier 27 is such that output 24 has an inverse polarity with respect to input 22 and the output 25 has an inverse polarity with respect to input 23. Hence, the feedbacks by resistors R₂ and R₄ are both negative. Assuming that the voltage between input terminals 20 and 21 is defined to be V₁ and the voltage between outputs 24 and 25 is defined to be V₂, the following equation between V₁ and V₂ should hold when the gain of the two-phase differential amplifier 27 is high enough: ##EQU1## If ##EQU2## then ##EQU3## Hence, V₂ is proportional to V₁ and a current in the normal or reverse direction flows in the load 26 correspondingly to either plus V₁ or minus V₁. Since, load 26 is not provided with a common terminal corresponding to the neutral point, the supply voltage is supplied thoroughly effectively to the load.

A modified embodiment of the invention is shown in FIG. 4, in which either output 24 or 25 is grounded alternatively by switch S₁ or S₂ and the other output which is not grounded actively constitutes a negative feedback circuit. Outputs 24 and 25 of two-phase differential amplifier 28 corresponding to the two-phase differential amplifier 27 have the correct polarity to be fed back to inputs 22 and 23 through transistors Q₁ and Q₂ and resistors R₂ and R₄.

The two following circuits are constructed in dependence upon how the switches S₁ and S₂ are switched.

(a) When output 241 makes transistor Q₁ active, switch S₁ is simultaneously opened, at which time output 251 is in a condition to turn off transistor Q₂ and simultaneously switch S₂ is closed. On the other hand, when output 251 makes transistor Q₂ active, switch S₂ is simultaneously opened, and output 241 turns off transistor Q₁ and simultaneously close switch S₁ is closed.

(b) When output 241 makes transistor Q₁ active, switch S₂ is simultaneously closed, at which time output 251 is in a condition to turn off transistor Q₂ and simultaneously switch S₁ is opened. On the other hand, when output 251 makes transistor Q₂ active, switch S₁ is closed and when output 241 turns-off transistor Q₁, simultaneously switch S₂ is opened.

In either case (a) or (b) above, the same effect is obtained. In other words, referring to FIG. 4, when the voltage V₁ between the input terminals 20 and 21 is positive (in the condition of keeping input terminal 20 higher in voltage than input terminal 21), transistor Q₁ is off and switch S₁ is closed. In this instance, only the transistor Q₂ is active; hence, assuming that the gain of two-phase differential amplifier 28 is high enough, the following relationship is obtained between the input voltage V₁ and the output voltage V₂ : ##EQU4## where V_(o) =the voltage at input terminal 21.

If ##EQU5## then ##EQU6## On the other hand, when the voltage between the input terminals 20 and 21 is negative, transistor Q₂ is off, and switch S₂ is simultaneously closed, thereby forming a negative feedback circuit with transistor Q₁. In this instance, if the same assumption as that noted above is made with respect to resistors R₁, R₂, R₃ and R₄, the relationship between V₁ and V₂ is always: ##EQU7## thereby keeping a linear operation.

Consequently, the switch S₁ or S₂ is switched correspondingly to input voltage V₁ and the output voltage V₂ always becomes ##EQU8## so that currents in the normal and reverse directions flow in load 26. Since the supply voltage, as seen from the above, is supplied to a load through transistor Q₁ or Q₂, the supply voltage as a whole is always in effective use.

In the description of FIGS. 3 and 4, the assumption of ##EQU9## is introduced between resistors R₁ through R₄, and the assumption is easy to realize especially when this invention is practically applied to an integrated circuit. The reason for this is that in an integrated circuit, it is possible to arrange the proportionality of resistors on the same chip with a high accuracy.

FIG. 5 shows an embodiment of this invention, which is applied to an integrated circuit. In a case (a), transistors Q₃ and Q₄ constitute a differential amplifier, in which the transistors have their emitters connected in common. Base 22 of the transistor Q₁ is connected to input terminal 20 through resistor R₃ and base 23 of transistor Q₄ is connected to input terminal 21 through resistor R₃. The collectors of transistors Q₃ and Q₄ are respectively connected to power source +V_(cc) through resistors R₅ and R₆. PNP transistors Q₅ and Q₆, whose emitters are connected to power source +V_(cc), have their bases respectively connected to the collectors of transistors Q₃ and Q₄. The collectors of transistors Q₅ and Q₆ are respectively connected to the bases 30 and 31 of transistors Q₂ and Q₁ whose collectors are connected to the power source. The bases and emitters of PNP transistors Q₇ and Q₈, whose collectors are grounded, are respectively connected in common to the bases and emitters of transistor Q₂ and Q₁, and the common emitters of transistors Q₂ and Q₇ constitue the output 25 and the common emitters of transistors Q₁ and Q₈ constitute the output 24, so that load 26 is interconnected between said outputs 24 and 25. The outputs 24 and 25 are respectively connected to bases 22 and 23 of transistors Q₃ and Q₄ through resistors R₂, R₄. The emitters of transistors Q₉, Q₁₀, and Q₁₁, whose bases are connected in common to bias terminal 29, are grounded through resistors R₇, R₈, and R₉, thereby constituting a constant current source. The collector of transistor Q₉ is connected to the common emitters of transistors Q₃ and Q₄. The collectors of transistors Q₁₀ and Q₁₁ are respectively connected to the bases 30 and 31 of transistors Q₂ and Q₁. The collector currents of transistors Q₁₀ and Q₁₁ are set so that the emitter current of switching transistor Q₇ or Q₈ when turned on, becomes a desired load current. The collector current of transistor Q₉ is so set that the collector currents of transistors Q₅ and Q₆, when the collector currents of transistors Q₃ and Q₄ are equal, become respectively equal to or slightly smaller than the collector currents of transistors Q₁₀ and Q₁₁.

In the aforesaid construction, if we assume that ##EQU10## when the input terminals 20 and 21 are equal in voltage, then transistors Q₁ and Q₂ are both become off, whereby both transistors Q₇ and Q₈ are off or in the condition of being slightly on.

At this time, if the voltage at input terminal 20 is made higher than that of input terminal 21, then transistor Q₃ increases in its collector current more than transistor Q₄ differentially. Hence, the collector current of transistor Q₅ becomes larger than that of transistor Q₁₀, and transistor Q₇ is off so as to make transistor Q₂ active. At the same time the, collector current of transistor Q₆ decreases so as to be further smaller than that of transistor Q₁₁, whereby, since transistor Q₁ is off, transistor Q₆ increases its base current so as to be in a condition of being further on. Thus, output 24 is grounded through transistor Q₈, so that the supply voltage +V_(cc) as a whole is fed to load 26. SInce output terminal 25 is in negative feedback through resistor R₄, the voltage at both ends of load 26 is proportional to the input so as to thereby satisfy the equation 1.

On the other hand, when the voltage at input terminal 20 is smaller than that at input terminal 21, the collector current of transistor Q₄ becomes larger than that of transistor Q₃. As a result, the collector current of transistor Q₆ increases and that of transistor Q₅ decreases. Hence, transistor Q₈ is off so as to make transistor Q₁ active and transistor Q₂ is off so that transistor Q₇ is in condition of being further on. Output terminal 25 is grounded through transistor Q₇ and output terminal 24 is put in the negative feedback through resistor R₂, whereby the voltage at both ends of the load 26 is also proporational to the input, thereby also satisfying the equation 1.

Consequently, output terminal 24 or 25 is alternatively grounded by switching transistors Q₇ or Q₈ in correspondence with the input voltage, thereby effectively using the whole supply voltage to enable the supply of currents in the normal and reverse directions to load 26.

FIG. 6 shows another modified embodiment corresponding to FIG. 5, in which resistors R₅ and R₆ in FIG. 5 are respectively replaced by diodes Q₁₂ and Q₁₃, (the diodes Q₁₂ and Q₁₃ shown as diode connected transistors), so that combination of transistor Q₅ with diode Q₁₂ and that of transistor Q₆ with diode Q₁₃, respectively constitute current mirrors. This embodiment operates in the same fashion as in the embodiment shown in FIG. 5.

FIG. 7 shows another modified embodiment in the aforesaid case (b), in which transistors Q₇ and Q₈ in FIG. 5 are respectively replaced by NPN transistors Q₂₂ and Q₂₃ ; the emitter of transistor Q₂₂ is grounded and its collector is connected to an output terminal 25 and its base is connected to the collector 31 of transistor Q₆ through resistor R₁₅. Transistor Q₂₃ has its emitter grounded, its collector connected to output terminal 24, and its base connected to collector 30 of transistor Q₅ through a resistance R₁₃. The bases of transistors Q₁ and Q₂ are respectively connected to collectors 31 and 30 through resistors R₁₄ and R₁₂. The constant current source transistors Q₉, Q₁₀ and Q₁₁ are set as follows: When the collector currents of transistors Q₃ and Q₄ are equal, resistances R₇, R₈ and R₉ are so set that the collector currents of transistors Q₅ and Q₆ are respectively equal to or slightly more than those of transistors Q₁₀ and Q₁₁. When either transistor Q₃ or Q₄ is off, transistor Q₅ or Q₆ drives transistor Q₂ or Q₁ to set the collector current of transistor Q₉ so that the load 26 is supplied with its required current. In this instance, when voltage at input terminal 20 is higher than that an input terminal 21, the collector current of transistor Q₅ become more than that of transistor Q₁₀, thereby making transistor Q₂ and Q₂₃ active. The selection of the values of resistors R₁₂ and R₁₃ enables transistor Q₂₃ to be saturated, whereby output terminal 24 is grounded through transistor Q₂₃ and output terminal 25 leads to linear operation by the negative feedback circuit. In an inverse relationship of the voltage at the input terminals, the effect of the invention can be expressed by the same description as that noted above. In addition, the embodiment in FIG. 7 also is suitable for manufacturing as an integrated circuit.

FIG. 8 shows a further modified embodiment, in which the PNP switching transistors Q₇ and Q₈ in FIGS. 5 and 6 respectively employ composite transistors. In FIG. 8, the base of PNP transistor Q₁₄ is connected to the collector of transistor Q₅, the collector of transistor Q₁₄ is connected to the base of NPN transistor Q₁₅, and the emitter of transistor Q₁₄ is connected to the power source +V_(cc) ; the emitter of transistor Q₁₅ is grounded its collector is connected to output terminal 25. Furthermore, one or more series diodes D₁ and D₂ are connected so that their anode is connected to the emitter of transistor Q₁₄ and their cathode is connected to output terminal 25. The base of PNP transistor Q₁₆ is connected to the collector of transistor Q₆, the collector of transistor Q₁₆ is connected to the base of NPN transistor Q₁₇, and the emitter of transistor Q₁₆ is connected to power source +V_(cc) through resistor R₁₇ ; the emitter of transistor Q₁₇ is grounded and its collector is connected to output terminal 24. Furthermore, one or more series diodes D₃ and D₄ are connected so that their anode is connected to the emitter of transistor Q₁₆ and their cathode is connected to output terminal 24. In this instance, transistors Q₁₅ and Q₁₇ act as the switching transistors. The operation of Q₁₄ and Q₁₅ when on, will be described with reference to FIG. 9. If the series forward voltage of diodes D₁ and D₂ which are forward biased by resistor R₁₆, is expressed by V_(D), and the collector voltage of transistor Q₁₅ is expressed by V_(S), and the base voltage of transistor Q₁₄ expressed by V_(A), and the voltage between emitter and base of transistor Q₁₄ expressed by V_(B), then the following equation is obtained:

    V.sub.A =V.sub.S +V.sub.D -V.sub.B ≧V.sub.S

Accordingly, the inequality V_(A) >0, even in a fully saturated condition of transistor Q₁₅, allows the constant current source transistor Q₁₀ not to be saturated, thereby sufficiently driving the base of transistor Q₁₄. In other words, output terminal 25 is grounded through transistor Q₁₅, so that output terminal voltage is sufficiently lowered, thereby effectively utilizing the supply voltage. Especially in an integrated circuit, it is possible to interpose resistors between the base and the emitter of the respective transistors Q₁₅ and Q₁₇ in order to prevent a malfunction in transistors Q₁₅ and Q₁₇ caused by leakage current. Furthermore, a constant current source may be used instead of resistors R₁₆ and R₁₇ to bias diodes D₁ through D₄ to thereby obtain the same effect.

In FIG. 4, switches S₁ and S₂ are interposed between the outputs 24 and 25 and the negative side of power source. Alternatively, switches S₃ and S₄ are interposed between the outputs corresponding respectively thereto and the positive side of power source, and transistors Q₁₈ and Q₁₉ are used, thereby obtaining a similarly operable construction (see FIG. 10).

FIG. 11 shows a still further modified embodiment which can detect a load current, in which transistors Q₁ and Q₂ respectively correspond to transistors Q₁ and Q₂ in FIG. 5, but the collectors of both transistors are connected in common and to power source +V_(cc) through resistor R₁₀, whereby the current values in the normal and reverse direction with respect to load 26 can be detected as the voltage across the ends 32 and 33 of resistor R₁₀, that is, the absolute value of the load current is detectable. Alternatively, the collectors of the transistors are connected directly to power source +V_(cc), and a resistor R₁₀ is interposed between the joint of common collectors of transistors Q₇ and Q₈ and ground, thereby apparently obtaining the same effect as in FIG. 11.

In addition, it is of sourse possible to apply various transformations to the transistor's conductivity, polarity of power cource, and the number of stages of amplification, without changing the principle of the invention, or to form other embodiments of these transformations.

As seen from the above description, the differential output circuit of the invention, even when applied to output circuits of other electronic circuits, can feed current to the load in the normal or reverse direction with only a single power source the use of the two-phase differential amplifier and negative feedback circuit, thereby having the effect of simultaneously using the whole supply voltage and being of an extremely high industrial value. 

What is claimed is:
 1. A differential output circuit comprising: a two-phase differential amplifier which has a first output which changes its output voltage in response to a voltage applied to a first input and has a second output which changes its output voltage in response to a voltage applied to a second input, said differential amplifier being driven by a single power source; a load which is connected between said first and second outputs, said first output and first input being connected together by a first negative feedback resistor, said second output and second input being connected together by a second negative feedback resistor; a first resistor and a second resistor are respectively connected at one end thereof with said first and second inputs; wherein said load is supplied with current flowing either in a normal or reverse direction according to the polarity of a potential difference between the other ends of said first and second resistors.
 2. A differential output circuit according to claim 1, further comprising first and second switches which are respectively interposed between said first and second outputs and a negative pole of said power source, wherein said first and second switches are driven so as to connect said first output with said negative pole of said power source when said potential difference between the other ends of said first and second resistors is positive or zero, and are driven so as to connect said second output with said negative pole of said power source when said potential difference is negative or zero.
 3. A differential output circuit according to claim 1, further comprising third and fourth switches which are respectively interposed between said first and second outputs and a positive pole of said power source, wherein said third and fourth switches are driven so as to connect said second output with said positive pole of said power source when said potential difference between the other ends of said first and second resistors is positive or zero, and driven so as to connect said first output with said positive pole of said power source when said potential difference is negative or zero.
 4. A differential output circuit according to claim 2 or claim 3, wherein transistors comprise said switches.
 5. A differential output circuit according to claim 1, further comprising a resistance which is interposed between said first and second outputs supplying current to said load and either one of positive and negative poles of said power source, wherein load current flows in common from said first and second outputs, thereby detecting the absolute value of said load current. 